Analyst Ming-Chi Kuo has echoed different reviews that Apple is anticipated to make use of a brand new chip packaging expertise within the A20 chip, which can debut within the iPhone 18 subsequent 12 months. His report focuses on suppliers for chip packaging supplies, relatively than the advantages of the brand new course of. We heard the identical from analyst Jeff Pu a pair months in the past.
While you purchase an iPhone 16 right this moment, the A19 chip inside is a fairly large and sophisticated monolithic “system on a chip.” It’s acquired the CPU, GPU, Neural Engine, video and audio encoders and decoders, and a bunch of different little stuff all on one massive advanced piece of silicon with round 30 billion transistors. Many chips are made on an enormous silicon disk (known as a wafer) after which packaged up and lower into particular person A19 chips, known as “dies.”
However the RAM is just not on the identical piece of silicon. RAM is usually manufactured utilizing completely different silicon processes, on completely different massive wafers, lower into their very own dies. Then the RAM is mixed with the massive SoC by connecting the 2 collectively utilizing one other piece of silicon, known as an interposer.
That is executed as a result of the manufacturing processes that produces SRAM effectively is completely different than what produces logic effectively. However with a brand new TSMC expertise known as “Wafer-Degree Multi-Chip Module (WMCM) packaging,” that may all change.
This course of will make it doable for Apple to construct an enormous monolithic chip that consists of the RAM on the identical die because the CPU, GPU, Neural Engine, media encoders, and so forth. If the present rumors are appropriate, this could be 12GB of RAM, however the course of doesn’t require any certain quantity. Rumors level to the iPhone 18 as the primary machine to make use of the brand new chip, and the iPhone Fold is also a candidate.
On-die RAM could simplify the manufacturing course of, requiring fewer steps than the present RAM-on-interposer setup. However the profit for customers is the potential to have very large and quick RAM interfaces, making entry to RAM nearly as quick as a high-level SRAM cache. This might drastically enhance efficiency in conditions which might be restricted by reminiscence bandwidth, akin to high-performance 3D graphics or sure AI functions.
It may additionally enable for higher energy administration, permitting the SoC with built-in RAM to make use of much less energy than the present setup with RAM connected on an interposer. This will enhance battery life, however battery life is an element of many various elements just like the show, wi-fi radios, storage, and extra.
